1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for driving the nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device in which a memory cell for storing information has a capacitor insulating film of a ferroelectric material, and a method for driving the nonvolatile semiconductor memory device.
2. Description of the Related Art
In nonvolatile semiconductor memory devices using a ferroelectric film (e.g. PZT (PbZrTiO.sub.3) or the like) for the capacitor insulating film of a memory cell, the hysteresis characteristics of polarization caused in the ferroelectric are utilized, and the information is stored by the remanent polarization of the ferroelectric film in a nonvolatile manner. In such nonvolatile semiconductor memory device, a memory cell for storing information of 1 bit usually includes two capacitors with ferroelectric films and two switching elements (transistors). In order to reduce the chip area and to increase the density of integrated circuits, a nonvolatile semiconductor memory device using a memory cell having one capacitor and one transistor (1C-1Tr memory cell) has been proposed (Japanese Laid-Open Patent Publication No. 5-75072).
FIG. 9 shows a part of the circuitry of a conventional nonvolatile semiconductor memory device 200 using the 1C-1Tr memory cell. As shown in FIG. 9, in the nonvolatile semiconductor memory device 200, a number of bit lines extending along the row direction are arranged in parallel in a column direction. A number of word lines WL.sub.0 -WL.sub.n-1 extend perpendicular to the bit lines (i.e., along the column direction) and are arranged in parallel in the row direction. In the read operation, one of the word lines WL.sub.0 -WL.sub.n-1 is selected in accordance with a row address, so as to be at a high potential level. In addition, two dummy word lines DWL.sub.0 and DWL.sub.1 are disposed in parallel to the word lines WL.sub.0 -WL.sub.n-1. The dummy word line DWL.sub.0 goes high when one of every other word lines (even-numbered word lines) WL.sub.0, WL.sub.2, . . . is selected. The dummy word line DWL.sub.1 goes high when one of the remaining word lines (odd-numbered word lines) WL.sub.1, WL.sub.3, . . . is selected.
Adjacent two bit lines BL.sub.i and BL.sub.i are paired (FIG. 9 shows the bit-line pairs of i=1, 2, 3, and 4).
To each pair of bit lines BL.sub.i and BL.sub.i, a sense amplifier 13, a bit-line equalizing circuit 11, a number of memory cells 6, and four dummy cells 7-10 are connected.
For each bit-line pair, respective memory cells 6 are disposed at crossings of one bit line BL.sub.i and the even-numbered word lines WL.sub.0, WL.sub.2, . . . , and crossings of the other bit line BL.sub.i and the odd-numbered word lines WL.sub.1, WL.sub.3, . . . . Two dummy cells 7 and 8 are disposed correspondingly to the bit line BL.sub.i and the dummy word line DWL.sub.1, and two dummy cells 9 and 10 are disposed correspondingly to the bit line BL.sub.i.
Next, the detailed circuitry of the nonvolatile semiconductor memory device 200 is described. FIG. 10 shows the circuitry of the sense amplifier 13 and the bit-line equalizing circuit 11. FIG. 10 shows pairs of bit lines BL.sub.i and BL.sub.i of i=1, 2, 3, and 4.
The sense amplifier 13 differentially amplifies a small potential difference between bit lines BL.sub.i and BL.sub.i by using four transistors Q.sub.31 -Q.sub.34, so as to make the signal level valid. Among the four transistors, Q.sub.31 and Q.sub.32 are N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and Q.sub.33 and Q.sub.34 are P-channel MOSFETs. The transistors Q.sub.31 and Q.sub.32 are connected to a ground potential level GND via an N-channel MOSFET Q.sub.35 of which the gate is connected to a sense-amplifier driving signal line S. The transistors Q.sub.33 and Q.sub.34 are connected to a V.sub.CC power supply via a P-channel MOSFET W.sub.36 of which the gate is connected to a sense-amplifier driving signal line S. The sense amplifier 13 performs its differential amplification only when the sense-amplifier driving signal lines S and S go high (V.sub.CC level) and low (GND level), respectively. As described later, in the read operation, after a small potential difference is read out from a memory cell 6 and the dummy cells 7-10 to the bit lines BL.sub.i and BL.sub.i, the sense-amplifier driving signal lines S and S go high and low, respectively by the operation of a control circuit (not shown).
The bit-line equalizing circuit 11 includes three P-channel MOSFETs Q.sub.111 -Q.sub.113. The source of the transistor Q.sub.111 is connected to the V.sub.CC power supply, and the drain thereof is connected to the bit line BL.sub.i. The source of the transistor Q.sub.112 is connected to the V.sub.CC power supply, and the drain thereof is connected to the bit line BL.sub.i. The drain of the transistor Q.sub.113 is connected to the bit line BL.sub.i, and the source thereof is connected to the other bit line BL.sub.i. The respective gates of the transistors Q.sub.111 -Q.sub.113 are connected to a bit-line equalizing signal line BEQ. The bit-line equalizing circuit 11 precharges the bit lines BL.sub.i and BL.sub.i to the supply voltage V.sub.CC by the transistors Q.sub.111 and Q.sub.112, and equalizes the potentials of the bit lines BL.sub.i and BL.sub.i by the transistor Q.sub.113, when the bit-line equalizing signal line BEQ goes low (in the ON state). Then, the bit-line equalizing signal line BEQ goes temporarily low immediately before the read operation by the operation of the control circuit (not shown).
As shown in FIG. 11, each memory cell 6 includes a capacitor C.sub.S having a ferroelectric film between the electrodes and an N-channel MOSFET Q.sub.S. One of the electrodes of the capacitor C.sub.S is connected to the bit line BL.sub.i or BL.sub.i via the source-drain of the transistor Q.sub.S. The other electrode of the capacitor C.sub.S is connected to a common cell plate to which a half voltage of the supply voltage V.sub.CC is supplied. The gate of the transistor Q.sub.S is connected to the corresponding one of the word lines WL.sub.0 -WL.sub.n-1.
As shown in FIG. 12., each of the dummy cells 7-10 includes a dummy capacitor C.sub.D having a ferroelectric film between the electrodes and an N-channel MOSFET Q.sub.D, similar to the memory cell 6. The dummy capacitor C.sub.D is formed so as to have a capacitance which is a half of that of the capacitor C.sub.S of the memory cell 6. One of the dummy capacitors C.sub.D is connected to one of the bit lines BL.sub.i and BL.sub.i corresponding to the respective dummy cells 7-10, via the source-drain of the transistor Q.sub.D. The other electrode of the dummy capacitor C.sub.D is connected to the common cell plate to which a half voltage of the supply voltage V.sub.CC is supplied. The gate of the transistor Q.sub.D is connected to one of the electrodes of the dummy word lines DWL.sub.0 and DWL.sub.1 corresponding to the dummy cells 7-10.
In each of the dummy cells 8 and 9, the connection node of one of the electrodes of the dummy capacitor C.sub.D and the source of the transistor Q.sub.D is grounded to the GND level via an N-channel MOSFET Q.sub.DN. The gate of the transistor Q.sub.DN is connected to a common dummy-cell precharge line PDUM. In each of the dummy cells 8 and 9, when the dummy-cell precharge line PDUM goes high, the ground voltage GND (0 V) is applied to one of the electrodes of the dummy capacitor C.sub.D.
In each of the dummy cells 7 and 10, the connection node of one of the electrodes of the dummy capacitor C.sub.D and the source of the transistor Q.sub.D is connected to the V.sub.CC power supply via a P-channel MOSFET Q.sub.DP. The gate of the transistor Q.sub.DP is connected to a dummy-cell precharge line PDUM. In each of the dummy cells 7 and 10, when the dummy-cell precharge line PDUM goes low, the supply voltage V.sub.CC is applied to one of the electrodes of the dummy capacitor C.sub.D. The dummy-cell precharge lines PDUM and PDUM go high and low, respectively by the operation of the control circuit (not shown), at the same time when the bit-line equalizing signal line BEQ goes low.
Next, the write operation and the read operation for the memory cells in the nonvolatile semiconductor memory device 200 are described. In the following explanation, a word line WL indicates any one of the word lines WL.sub.0 -WL.sub.n-1 selected in the write or read operation. A bit line BL indicates one of a pair of bit lines BL.sub.i and BL.sub.i selected at that time, and corresponding to the memory cell 6 connected to the selected word line WL.
When data "1" is to be written into the memory cell 6, as shown in FIG. 13, the word line WL is set high, while a supply voltage V.sub.CC is applied to the bit line BL. Accordingly, the transistor Q.sub.S is turned ON, and the supply voltage V.sub.CC of the bit line BL is applied to one of the electrodes of the capacitor C.sub.S. Since a half voltage of the supply voltage V.sub.CC is applied to the other electrode of the capacitor C.sub.S, a half voltage of the supply voltage V.sub.CC is applied across the electrodes of the capacitor C.sub.S (hereinafter, the polarity of the voltage in this state is assumed to be positive). To the ferroelectric film between the electrodes of the capacitor C.sub.S, a positive electric field E.sub.max corresponding to a positive half voltage of the supply voltage V.sub.CC is applied. Polarization charge P.sub.s is accumulated in the capacitor C.sub.S (FIG. 14).
Thereafter, the word line WL returns to a low level, and the transistor Q.sub.S is turned OFF. Then, due to a leakage current of the ferroelectric film in the capacitor, the electric potential levels of the two electrodes of the capacitor C.sub.S gradually become equal to each other. At this time, no electric field is applied to the ferroelectric film, but the ferroelectric film holds the remanent polarization charge P.sub.r. The remanent polarization charge P.sub.r can be held even when the supply of supply voltage to the nonvolatile semiconductor memory device is cut off and 1/2 V.sub.CC is not applied to the other end of the capacitor C.sub.S. Therefore, the memory cell 6 stores the data "1" as nonvolatile information by the remanent polarization charge P.sub.r.
When data "0" is to be written into the memory cell 6, as shown in FIG. 15, the word line WL is set high, while a ground voltage GND (0 V) is applied to the bit line BL. Accordingly, the transistor Q.sub.S is turned ON, and 0 V is applied to one of the electrodes of the capacitor C.sub.S. A half voltage of the supply voltage V.sub.CC of the polarity opposite to that of the above-mentioned case is applied across the electrodes of the capacitor C.sub.S (hereinafter, the polarity of the voltage is assumed to be negative). To the ferroelectric film between the electrodes of the capacitor C.sub.S, a negative electric field -E.sub.max corresponding to a negative half voltage of the supply voltage V.sub.CC is applied. Polarization charge -P.sub.s is accumulated in the capacitor C.sub.S (FIG. 16).
Thereafter, the word line WL returns to a low level, and the transistor Q.sub.S is turned OFF. Then, due to a leakage current of the ferroelectric film in the capacitor, the electric potential levels of the two electrodes of the capacitor C.sub.S gradually become equal to each other. At this time, no electric field is applied to the ferroelectric film, but the ferroelectric film holds remanent polarization charge -P.sub.r. The remanent polarization charge -P.sub.r can be held even when the supply of supply voltage is cut off and 1/2 V.sub.CC is not applied to the other end of the capacitor C.sub.S. Therefore, the memory cell 6 stores the data "0" as nonvolatile information by the remanent polarization charge -P.sub.r.
When the data stored in the memory cell 6 is to be read, the bit line BL is precharged to the supply voltage V.sub.CC prior to the read operation. After the supply voltage is applied and charge is sufficiently accumulated, the bit line is disconnected from the power supply, so as to complete the precharge.
The read operation when the data "1" is stored in the memory cell 6 is shown in FIG. 17. The word line WL is set high in the precharged state, and then the transistor Q.sub.S is turned ON. Accordingly, the charge of the bit line BL and the remanent polarization charge P.sub.r held in the ferroelectric film of the capacitor C.sub.S are charge-shared. In general, the capacitance C.sub.B of the bit line BL is sufficiently larger than the capacitance C.sub.S of the capacitor C.sub.S, so that a voltage substantially equal to the supply voltage V.sub.CC is applied to one of the electrodes of the capacitor C.sub.S. Therefore, a positive voltage substantially equal to a half of the supply voltage V.sub.CC is applied across the electrodes of the capacitor C.sub.S, so that, as shown in FIG. 18, an electric field E.sub.max corresponding to the positive voltage is applied to the ferroelectric film. Thus, polarization charge P.sub.s is accumulated in the ferroelectric film. As is seen from FIG. 18, polarization reversal is not caused in the ferroelectric film. The amount of charge moved from the bit line BL to the capacitor C.sub.S is P.sub.s -P.sub.r.
Accordingly, the potential variation .DELTA.V.sub.1 of the bit line BL, i.e., the read voltage level of the bit line L in the case where the data "1" is read out is given by Equation (1) below. ##EQU1##
The read operation when the data "0" is stored in the memory cell 6 is shown in FIG. 19. The word line WL is set high in the state precharged to the supply voltage V.sub.CC, and then the transistor Q.sub.S is turned ON. Accordingly, the charge of the bit line BL and the remanent polarization charge -P.sub.r held in the ferroelectric film of the capacitor C.sub.S are charge-shared. In general, the capacitance C.sub.B of the bit line BL is sufficiently larger than the capacitance C.sub.S of the capacitor C.sub.S, so that a voltage substantially equal to the supply voltage V.sub.CC is applied to one of the electrodes of the capacitor C.sub.S. Therefore, a positive voltage substantially equal to a half of the supply voltage V.sub.CC is applied across the electrodes of the capacitor C.sub.S, so that, as shown in FIG. 20, an electric field E.sub.max corresponding to the positive voltage is applied to the ferroelectric film. Thus, polarization charge P.sub.s is accumulated in the ferroelectric film. As is seen from FIG. 20, the polarization reversal is caused in the ferroelectric film. The amount of charge moved from the bit line BL to the capacitor C.sub.S is P.sub.s +P.sub.r.
Accordingly, the potential variation .DELTA.V.sub.0 of the bit line BL, i.e., the read voltage level of the bit line L in the case where the data "0" is read out is given by Equation (2) below. ##EQU2##
As described above, in the read operation, the read voltage level (the potential variation of the bit line BL) is different depending on the data stored in the memory cell 6. By detecting and amplifying the difference, it is possible to identify the stored data. In the nonvolatile semiconductor memory device 200, as described below, the read voltage level (potential variation) of one of a pair of bit lines BL.sub.i and BL.sub.i is compared with the potential variation of the other bit line by the dummy cells 7-10, so that the stored data is detected.
Next, by referring to FIG. 21, the specific procedure of the read operation in the nonvolatile semiconductor memory device 200 will be described.
First, prior to the read operation, at time t.sub.21, a low-pulse is input to the bit-line equalizing signal line BEQ (i.e., the line is kept at a low level for a predetermined time period), so that the bit-line equalizing circuit 11 is driven. That is, the P-channel transistors Q.sub.111 -Q.sub.113 are turned ON, and the bit lines BL.sub.i and BL.sub.i are precharged to the supply voltage V.sub.CC. In a synchronizing manner, at the time t.sub.21, a high-pulse is input into the dummy-cell precharge line PDUM (i.e., the line is kept at a high level for a predetermined time period), so that a ground voltage GND (0 V) is applied to one of the electrodes of the dummy capacitor C.sub.D in each of the dummy cells 8 and 9. Similarly, a low-pulse is input into the dummy-cell precharge line PDUM, so that the supply voltage V.sub.CC is applied to one of the electrodes of the dummy capacitor C.sub.D in each of the dummy cells 7 and 10.
When 0 V is applied to one of the electrodes of the dummy capacitor C.sub.D, a negative half voltage of the supply voltage V.sub.CC is applied across the electrodes of the dummy capacitor C.sub.D. Accordingly, similarly to the case where the data "0" is written into the memory cell 6, the ferroelectric film is polarized in a negative direction. When the supply voltage V.sub.CC is supplied to one of the electrodes of the dummy capacitor C.sub.D, a positive half voltage of the supply voltage V.sub.CC is applied across the electrodes of the dummy capacitor C.sub.D. Accordingly, similar to the case where the data "1" is written into the memory cell 6, the ferroelectric film is polarized in a positive direction. Therefore, the ferroelectric films of the dummy capacitors C.sub.D in the two dummy cells (7 and 8, or 9 and 10) connected to one bit line (BL.sub.i or BL.sub.i) are polarized in directions opposite to each other. Since the capacitance of the capacitor C.sub.D in each of the dummy cells 7-10 is half of the capacitance of the capacitor C.sub.S in the memory cell 6, in the case where an identical voltage is applied, the charge held in the dummy capacitor C.sub.D is a half of the charge held in the capacitor C.sub.S.
Next, at time t.sub.22 at which the read operation starts, any one word line WL of the word lines WL.sub.0 -WL.sub.n-1 is selected to be set high and the transistor Q.sub.S of the memory cell 6 connected to the word line WL is turned ON. When data "1" is stored in the memory cell 6, as described above, the charge corresponding to (P.sub.s -P.sub.r) moves from the bit line BL to the capacitor C.sub.S. As a result, the potential level of the bit line BL is lowered from the supply voltage V.sub.CC by the potential variation .DELTA.V.sub.1 expressed by Equation (1). When data "0" is stored in the memory cell 6, as described above the charge corresponding to (P.sub.s +P.sub.r) moves, so that the potential level of the bit line BL which is connected to the memory cell 6 is lowered from the supply voltage V.sub.CC by the potential variation .DELTA.V.sub.0 expressed by Equation (2). As is apparent from FIGS. 18 and 20, the potential variation .DELTA.V.sub.1 is relatively small and the potential variation .DELTA.V.sub.0 is significantly large.
At time t.sub.22, any one dummy word line DWL corresponding to the selected word line WL is also set high. That is, when the memory cell 6 connected to the selected word line WL is connected to one bit line BL.sub.i, the dummy word line DWL.sub.0 of the dummy cells 9 and 10 connected to the other bit line BL.sub.i is set high. When the memory cell 6 is connected to the other bit line BL.sub.i, the dummy word line DWL.sub.1 of the dummy cells 7 and 8 connected to the bit line BL.sub.i is set high.
In the above-described manner, when one dummy word line DWL goes high, transistors Q.sub.D in either pair of dummy cells 7 and 8 or dummy cells 9 and 10 are turned on. As to the dummy cells 7 and 10, the charge movement which is identical with the case where the data "1" is stored in the memory cell 6 occurs. As to the dummy cells 8 and 9, the charge movement which is identical with the case where the data "0" is stored in the memory cell 6 occurs. However, the capacitance of the dummy capacitor C.sub.D is set to be a half of the capacitance of the capacitor C.sub.S of the memory cell 6, so that the amount of charge moving from the bit line BL to the dummy capacitor C.sub.D of the dummy cell 7 or 10 is (P.sub.s -P.sub.r)/2 and the amount of charge moving from the bit line BL to the dummy capacitor C.sub.D of the dummy cell 8 or 9 is (P.sub.s +P.sub.r)/2. Accordingly, the total amount of charge moving from the bit line BL to the pair of dummy cells 7 and 8 or 9 and 10 is P.sub.s in any case. Thus, the potential variation .DELTA.V.sub.D of the bit line BL by a pair of dummy cells is constant as expressed by Equation (3) below. ##EQU3##
The potential variation is indicated by two-dot chain line in FIG. 21.
Therefore, in the case where the data "1" is stored in the memory cell 6, at the time after a short time elapses from time t.sub.22, there occurs a potential difference .DELTA.V.sub.dif1 expressed by Equation (4) below between the pair of bit lines BL.sub.i and BL.sub.i as a difference between Equation (1) and Equation (3). The potential difference .DELTA.V.sub.dif1 is input into and amplified by the sense amplifier 13 (which is described later). ##EQU4##
In the case where the data "0" is stored in the memory cell 6, there occurs a potential difference .DELTA.V.sub.dif0 expressed by Equation (5) below as a difference between Equation (2) and Equation (3). The potential difference .DELTA.V.sub.dif0 is input into and amplified by the sense amplifier 13 (which is described later). ##EQU5##
As described above, between the pair of bit lines BL.sub.i and BL.sub.i either one of potential differences having opposite polarities and the same absolute values occurs depending on the data stored in the memory cell 6 is "1" or "0". By amplifying the potential difference to a predetermined level by the sense amplifier 13 in the following manner, the data "1" and "0" can be identified.
At time t.sub.23, the sense-amplifier driving signal lines S and S go high and low, respectively. As a result, the sense amplifier 13 is driven so as to differentially amplify the potential difference. Then, the potential levels of the pair of bit lines BL.sub.i and BL.sub.i are changed to the supply voltage .sub.CC and the ground voltage GND, respectively, based on the polarity of the potential difference, so as to make the signal level valid. By reading the signal levels of the pair of bit lines BL.sub.i and BL.sub.i, the data stored in the selected memory cell 6 can be identified and output. That is, the digital value which is stored in a nonvolatile manner can be read out without fail.
As shown in FIG. 21, the high-level voltage applied to the word line WL and the dummy word line DWL is set higher than the supply voltage V.sub.CC by a threshold voltage V.sub.th of the transistor Q.sub.S and the transistor Q.sub.D. This setting makes it sure to apply a supply voltage V.sub.CC of the bit line BL to one of the electrodes of each of the capacitor C.sub.S and the dummy capacitor C.sub.D.
Next, the construction of a conventional nonvolatile semiconductor memory device for storing 1-bit information to a memory cell having two capacitors and two transistors (2C-2Tr) is described. The construction of such a 2C-2Tr memory cell 12 is shown in FIG. 22.
The memory cell 12 includes two N-channel MOSFETs Q.sub.S1 and Q.sub.S2 and two capacitors C.sub.S1 and C.sub.S2 each having a ferroelectric film between the electrodes. One of the electrodes of the capacitor C.sub.S1 is connected to one bit line BL.sub.i via the source and drain of the transistor Q.sub.S1. One of the electrodes of the capacitor C.sub.S2 is connected to the other bit line BL.sub.i via the source and drain of the transistor Q.sub.S2. The other electrodes of the capacitors C.sub.S1 and C.sub.S2 are both connected to a drive line DL. The gates of the transistors Q.sub.S1 and Q.sub.S2 are both connected to the corresponding word line WL.
The operation for writing data "1" into the memory cell 12 is performed in the following manner. First, a supply voltage V.sub.CC is applied to one bit line BL.sub.i, and a ground voltage GND is applied to the other bit line BL.sub.i. After the word line WL is set high, and hence the transistors Q.sub.S1 and Q.sub.S2 are turned ON, a pulse voltage is applied to the drive line DL. The pulse signal changes from the ground voltage GND to the supply voltage V.sub.CC and then back to the ground voltage GND. Due to the pulse signal, an electric field E.sub.VCC corresponding to the supply voltage V.sub.CC is applied across the electrodes of the capacitor C.sub.S1, when the drive line DL is at the ground voltage GND. A negative electric field -E.sub.VCC corresponding to a negative supply voltage -V.sub.CC is applied across the electrodes of the capacitor C.sub.S2, when the drive line DL is at the supply voltage V.sub.CC. As a result, the ferroelectric films of the capacitors C.sub.S1 and C.sub.S2 are polarized to P.sub.s and -P.sub.s, respectively. After the level of the drive voltage returns to the ground voltage GND and the transistors Q.sub.S1 and Q.sub.S2 are turned OFF, the remanent polarization charges P.sub.r and -P.sub.r are held (FIG. 23).
When the data "0" is to be written, similarly, the supply voltage V.sub.CC is applied to the bit line BL.sub.i, and the ground voltage GND is applied to the other bit line BL.sub.i. As a result, the ferroelectric films of the capacitors C.sub.S1 and C.sub.S2 hold the remanent polarization charges -P.sub.r and P.sub.r of the polarities opposite to those in the case of the writing of the data "1". As described above, the ferroelectric films of the two capacitors C.sub.S1 and C.sub.S2 hold remanent polarization charges of polarities opposite to each other, so that the 1-bit information is stored in the nonvolatile manner.
The data stored in the memory cell 12 is read out in the following manner. First, the bit lines BL.sub.i and BL.sub.i are precharged to the ground voltage GND. That is, the bit lines BL.sub.i and BL.sub.i are connected to the ground voltage GND so as to sufficiently release the charge, and then disconnected, i.e., the discharge is performed. The word line WL is set high in the discharged state, and then the transistor Q.sub.S is turned ON. A stepped voltage which changes from the ground voltage GND to the supply voltage V.sub.CC is applied to the drive line DL. When the potential level of the drive line DL reaches the supply voltage V.sub.CC, a negative electric field -E.sub.VCC corresponding to the supply voltage V.sub.CC of the opposite polarity is applied between the electrodes of the two capacitors C.sub.S1 and C.sub.S2. Thus, the ferroelectric films of the capacitors C.sub.S1 and C.sub.S2 are polarized to P.sub.s and -P.sub.s, respectively.
When the data "1" is stored in the memory cell 12, as shown in FIG. 24, the charge of the bit line BL.sub.i and the remanent polarization charge P.sub.r held in the ferroelectric film of the capacitor C.sub.S1 are charge-shared and the charge of the bit line BL.sub.i and the remanent polarization charge -P.sub.r held in the ferroelectric film of the capacitor C.sub.S2 are charge-shared. At this time, as seen from FIG. 24, the polarization reversal does not occur in the ferroelectric film of the capacitor C.sub.S2. Thus, a difference expressed as P.sub.s +P.sub.r -(P.sub.s -P.sub.r)=2P.sub.r occurs between the amounts of charges from the capacitors C.sub.S1 and C.sub.S2 to the bit lines BL.sub.i and BL.sub.i, respectively. Accordingly, a minute potential difference appears between the bit lines BL.sub.i and BL.sub.i. This potential difference is amplified by a sense amplifier 13, so that the data stored in the memory cell 12 is read out.
In the case where the data "0" is stored in the memory cell 12, the polarization reversal does not occur in the ferroelectric film of the capacitor C.sub.S1, but occurs in the ferroelectric film of the capacitor C.sub.S2. Between the bit lines BL.sub.i and BL.sub.i, there appears a minute potential difference of the polarity which is opposite to that of the case where the data "1" is stored. The potential difference is amplified by the sense amplifier 13, so that the data stored in the memory cell 12 is read out.
As described above, in the conventional nonvolatile semiconductor memory device 200, the data read from the memory cell 6 is a so-called "destructive read". That is, in the read of data, the electric field E.sub.max is applied to the ferroelectric film of the capacitor C.sub.S. Therefore the polarization charge P.sub.s is accumulated in the capacitor C.sub.S, so that the held remanent polarization charge P.sub.r or -P.sub.r corresponding to the data "1" or "0" is lost (see FIGS. 18 and 20).
In the nonvolatile semiconductor memory device using the above-described 2C-2Tr memory cell, similarly, the destructive read is performed. That is, a negative electric field -E.sub.VCC is uniformly applied to the ferroelectric films of both the capacitors C.sub.S1 and C.sub.S2 during the read operation, so that the remanent polarization charge P.sub.r or -P.sub.r of different polarities corresponding to the data "1" or "0" is lost (FIG. 24).
Therefore, after the read operation, it is necessary to perform a rewrite operation for writing the read-out data into the memory cell again by utilizing the valid signal levels of the bit lines BL.sub.i and BL.sub.i.
In general, a semiconductor memory device includes a row decoder for selecting a word line having a specific row address and a column decoder for selecting a bit-line pair having a specific column address. A memory cell which is disposed at the crossing of the selected word line and the bit-line pair is specified (i.e., the row address and the column address are specified), and the write and read operations are performed for the specified memory cell.
In the conventional nonvolatile semiconductor memory cell 200, when any one word line WL is selected and set high, the data of all memory cells 6 connected to the selected word line WL are destructively read out onto the respective bit lines BL and BL.sub.i. In other words, the data is destroyed as the result of the data read for the memory cells of which the data are not required. Accordingly, in order to hold the stored data, it is necessary to perform the rewrite of the data read out on the bit lines for all of the memory cells connected to the selected word lines WL. In order to perform the rewriting, it is necessary to drive the sense amplifiers 13 connected to all of the bit lines BL BL. This results in waste power consumption because the amplification and rewrite are performed for the bit-line pairs for which the data read are not required. Thus, the consumed power is disadvantageously increased. This problem is also caused in the nonvolatile semiconductor memory cell having 2C-2Tr memory cells.